1. Field of the Invention
The present invention relates in general to a method of manufacturing a semiconductor memory and in particular to a method of manufacturing a large-capacity NAND-type mask ROM with submicrometer gates.
2. Description of the Related Art
A method of producing a NAND-type mask ROM is presented in Japanese Patent Laid-open No. 62-92362, in which data programming is performed through ion implantation. The method as a representative case of the prior art will be explained with reference to FIGS. 1 through 3 of the accompanying drawings.
As shown in FIG. 1, a field oxide 2 is first formed on a P-type silicon substrate 1 by the LOCOS method, and then a gate oxide 3 is formed on the substrate. Next, a polysilicon is deposited over the entire surface of the layers formed by the preceding steps and selectively etched to form polysilicon gate electrodes 4a through 4e, using a photoresist as a mask.
N.sup.+ -type diffusion layers 9a through 9g are then formed in the P-type silicon substrate 1 by ion implantation using gate electrodes 4a through 4e as masks.
Next, photoresist 10 is formed in the manner shown in FIG. 2, in which openings 11 are provided above only each transistor or bit to which the data "ON" is to be written. These bits are hereafter referred to as data bits. Using photoresist 10 as a mask, phosphorus ions with an incident energy high enough to penetrate gate electrodes 4b and 4d are implanted into the silicon substrate, thereby forming N.sup.- doped channel layers 12b and 12e under the gate electrodes 4b and 4d, respectively. In this way, depletion-type MOSFETs are formed in the data bits which correspond to data-storing bits.
Next, as illustrated in FIG. 3, an interlayer dielectric 13 of PSG (Phospho-Silicate Glass) is formed over the existing surface, and a digit line contact 14 is opened above the N.sup.+ -type diffusion layer 9a through interlayer dielectric 13. Finally, a digit line 15 of aluminum is deposited both on the interlayer dielectric 13 and in the digit line contact 14, and a NAND-type mask ROM device provided with N.sup.+ -type single-drain MOSFETs in its memory cells and its peripheral circuits is obtained.
In the prior art above, when "ON" data is written by implanting the phosphorus ions through the gate electrodes to form the N.sup.- doped channel layers 12b, 12e N.sup.- doped layers 12a, 12c, 12d and 12f are also formed parasitically in the silicon substrate 1 underneath the source-drain diffusion layers, as shown in FIG. 2. These parasitically doped layers (hereafter, referred to as parasitic layers) allow junction depth X.sub.j of the sources and drains to be larger. As is well-known in the art, a MOSFET normally operates in response to a gate voltage, provided that the channel length L is sufficiently longer than the sum of the widths of the depletion layers in the source and drain junctions. However, when the scale of the device is reduced to the order of submicrometers, making the channel length L a critical value L.sub.min or less, punch-through tends to take place. According to an empirical law in the field of semiconductor devices, the critical channel length L.sub.min increases in proportion to (X.sub.j).sup.1/3. Accordingly, punch-through tends to occur as the junction depth X.sub.j increases, even if the actual channel length L remains unchanged. As a result, punch-through takes place between parasitic layers 12c and 12 d, i.e. across the channel region of the unwritten bit or "OFF" bit (9c, 9d, 4c), thereby generating a current path irresponsive to a control signal applied to gate electrode 4c. This leads to the problem that "OFF" data in the unwritten bit (9c, 9d, 4c) cannot be read.
Another problem arises from the fact that the foregoing semiconductor memory consists of N.sup.+ -type single drain transistors. As is well-known, when the channel length L is not sufficiently long in comparison with critical length L.sub.min, as is the case in a so-called submicrometer-scale device, hot carriers caused by a strong electric field between the drain and gate tend to be created between the gate electrode and drain. This creation of hot carrier brings about detrimental unstable behavior of the transistor which results in unreliable performance of the semiconductor device. This is the case in the peripheral circuit composed of an N.sup.+ -type single drain transistor (9f, 9g, 4e) shown in FIG. 3.
This tendency becomes more prominent, with higher doping levels in the N.sup.+ diffusion layers of the source and drain. Accordingly, when an N.sup.+ -type single-drain MOSFET is employed, the reliability of the device is a problem unless the power supply voltage is lowered according to pattern scaling.